Interrupts may be used to notify the device driver of asynchronous events—keyboard presses, incoming data traffic from a network adapter, completion of a read from/write to a storage device, and to notify the device driver of an error. In the case of storage and networking, to increase performance, the work can be divided among different threads, with each thread notified by one or more interrupts.
In Peripheral Component Interconnect (PCI) or PCI Express (PCIe) there are mainly two types of interrupt mechanisms: Legacy/Level Signaled Interrupts (LSIs) and Message Signaled Interrupts (MSIs). In case of the LSIs, an input/output (I/O) device has an interrupt pin which it asserts when the device wants to signal an interrupt to the host processing environment. This traditional form of interrupt signaling is an out-of-band form of control signaling since LSI uses a separate dedicated path relative to the main data path to send such control information. With complex I/O fabrics, however, the number of dedicated lines or pins that would be required to provide interrupt functionality for all of the I/O resources connected to the fabric may be impractical. As a result, more complex I/O fabrics may implement MSIs by writing data to specific memory addresses in the system address space. MSIs, which are in-band method of signaling an interrupt, allow the device to write a small amount of data to a special memory-mapped I/O address which is then delivered to the appropriate destination—e.g., a processor.
As an example of a computer system using MSIs, a PCI-enabled I/O device may issue MSIs as DMA writes where the DMA address is a MSI port in a PCI Host Bridge (PHB) and the DMA write data is an interrupt number selected from a range of interrupt numbers enabled at the MSI port. The PHB decodes the MSI port address on the PCI bus and uses the interrupt number in the DMA write data to present the PCI interrupt to the appropriate virtual machine or processor. To configure MSI in the I/O device, a Hypervisor presents the virtual machine with the MSI properties of the PHB. These properties consist of the number of MSI ports and the number of MSI interrupts the PHB provides. When the PHB supports multiple I/O devices, these MSI resources are divided amongst the virtual machines that control I/O devices connected to the PHB.